HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 498

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface (SCI)
13.7.2
Figure 13.22 shows the transfer data format in smart card interface mode.
• One frame consists of 8-bit data plus a parity bit in asynchronous mode.
• In transmission, a guard time of at least 2 etu (Elementary time unit: the time for transfer of
• If a parity error is detected during reception, a low error signal level is output for one etu
• If an error signal is sampled during transmission, the same data is retransmitted automatically
Data transfer with other types of IC cards (direct convention and inverse convention) should be
performed as described in the following.
With the direction convention type IC and the above sample start character, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The above start character data is H'3B. For the direct convention type, clear the DIR and SINV
Rev.4.00 Mar. 27, 2008 Page 452 of 882
REJ09B0108-0400
one bit) is left between the end of the parity bit and the start of the next frame.
period, 10.5 etu after the start bit.
after a delay of 2 etu or longer.
Data Format (Except for Block Transfer Mode)
When there is no parity error
When a parity error occurs
[Legend]
DS:
D0 to D7:
Dp:
DE:
Figure 13.22 Normal Smart Card Interface Data Format
Figure 13.23 Direct Convention (DIR = SINV = O/E = 0)
(Z)
Ds
Ds
Start bit
Data bits
Parity bit
Error signal
Ds
A
D0
D0
D0
Z
D1
D1
D1
Z
Transmitting station output
Transmitting station output
D2
D2
D2
A
D3
Z
D3
D3
D4
Z
D4
D4
D5
Z
D5
D5
D6
A
D6
D6
D7
A
Dp
Z
D7
D7
Dp
Dp
(Z)
Receiving station
output
State
DE