HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 183

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The bus state controller (BSC) divides up the address spaces and outputs control signals for
various types of memory. This enables memories like SRAM and ROM to be connected directly
to the chip without external circuitry.
9.1
The BSC has the following features:
• Address space is divided into four spaces
• On-chip ROM and RAM interfaces
BSC1001A_020020030800
⎯ A maximum linear 2 Mbytes for on-chip ROM enabled mode, and a maximum 4 Mbytes
⎯ A maximum linear 4 Mbytes for address space CS1 to CS3 and CS5 to CS7
⎯ Bus width (8, 16, or 32 bits) can be selected for each space
⎯ Wait states can be inserted by software for each space
⎯ Wait state insertion with WAIT pin in external memory space access
⎯ Outputs control signals for each space according to the type of memory connected
⎯ On-chip ROM and RAM access of 32 bits in 1 state
for on-chip ROM disabled mode, for address spaces CS0 and CS4
Features
Section 9 Bus State Controller (BSC)
Rev.4.00 Mar. 27, 2008 Page 137 of 882
9. Bus State Controller (BSC)
REJ09B0108-0400