HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 165

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The initial value of DTCRA is undefined.
8.2.6
The DTCRB is a 16-bit register that designates the block length in block transfer mode. The block
length is 1 when the set value is H'0001, 65535 when it is H'FFFF, and 65536 when it is H'0000.
The initial value of DTCRB is undefined.
8.2.7
DTER which is comprised of six registers, DTEA to DTEE, DTEG, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTE bits is
shown in table 8.1.
Note:
Bit
7
6
5
4
3
2
1
0
Bit Name
DTE*7
DTE*6
DTE*5
DTE*4
DTE*3
DTE*2
DTE*1
DTE*0
*
DTC Transfer Count Register B (DTCRB)
DTC Enable Registers (DTER)
Example: DTEB3 in DTEB, etc.
The last character of the DTC enable register’s name comes here.
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
DTC Activation Enable
Setting this bit to 1 specifies the corresponding
interrupt source to a DTC activation source.
[Clearing conditions]
•
•
•
These bits are not cleared when the DISEL bit is 0
and the specified number of transfers have not
ended.
[Setting condition]
1 is written to the bit to be set after a 0 has been read
from the bit
When the DISEL bit is 1 and the data transfer has
ended
When the specified number of transfers have
ended
0 is written to the bit to be cleared after 1 has
been read from the bit
Rev.4.00 Mar. 27, 2008 Page 119 of 882
8. Data Transfer Controller (DTC)
REJ09B0108-0400