HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 145

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.8.1
1. Do not select DMAC activating sources or clear the DTE bit to 0.
2. For DTC, set the corresponding DTE bits and DISEL bits to 1.
3. Activating sources are applied to the DTC when interrupts occur.
4. When the DTC performs a data transfer, it clears the DTE bit to 0 and sends an interrupt
5. The CPU clears interrupt sources in the interrupt processing routine then confirms the transfer
6.8.2
1. Select DMAC activating sources and set the DME bit to 1. Then, CPU interrupt and DTC
2. Activating sources are applied to the DMAC when interrupts occur.
3. The DMAC clears the interrupt sources when starting transfer.
6.8.3
1. Do not select DMAC activating sources or clear the DME bit to 0.
2. For DTC, set the corresponding DTE bits to 1 and clear the DISEL bits to 0.
3. Activating sources are applied to the DTC when interrupts occur.
4. When the DTC performs a data transfer, it clears the activating source. An interrupt request is
5. However, when the transfer counter value = 0 the DTE bit is cleared to 0 and an interrupt
6. The CPU performs the necessary end processing in the interrupt processing routine.
request to the CPU. The activating source is not cleared.
activating sources are masked regardless of the settings of the interrupt priority register and the
DTC register.
not sent to the CPU, because the DTE bit is hold to 1.
request is sent to the CPU.
counter value. When the transfer counter value is not 0, the CPU sets the DTE bit to 1 and
allows the next data transfer. If the transfer counter value = 0, the CPU performs the
necessary end processing in the interrupt processing routine.
Handling Interrupt Request Signals as Sources for DTC Activating and CPU
Interrupt, but Not DMAC Activating
Handling Interrupt Request Signals as Sources for Activating DMAC, but Not
CPU Interrupt and DTC Activating
Handling Interrupt Request Signals as Source for DTC Activating, but Not CPU
Interrupt and DMAC Activating
Rev.4.00 Mar. 27, 2008 Page 99 of 882
6. Interrupt Controller (INTC)
REJ09B0108-0400