HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 440

IC SUPERH MCU ROMLESS 112QFP

HD6417144F50V

Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet

Specifications of HD6417144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
13. Serial Communication Interface (SCI)
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart card interface
• Data is automatically retransmitted if an error signal is received while data is being transmitted
• Direct convention and inverse convention both supported
Note: * The description in this section is based on LSB-first transfer.
Figure 13.1 shows a block diagram of the SCI.
Rev.4.00 Mar. 27, 2008 Page 394 of 882
REJ09B0108-0400
RxD
TxD
SCK
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
SDCR: Serial direction control register
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
RDR
RSR
Figure 13.1 Block Diagram of SCI
Parity generation
Parity check
TDR
TSR
Module data bus
Transmission/
reception
control
SDCR
SMR
SCR
SSR
External clock
Clock
Baud rate
generator
BRR
TEI
TXI
RXI
ERI
Pφ/8
Pφ/32
Pφ/128
Internal
data bus

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