HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 213

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

This LSI includes an on-chip four-channel direct memory access controller (DMAC). The DMAC
can be used in place of the CPU to perform high-speed data transfers among external devices
equipped with DACK (transfer request acknowledge signal), external memories, memory-mapped
external devices, and on-chip peripheral modules (except for the DMAC, DTC, BSC, and UBC).
Using the DMAC reduces the burden on the CPU and increases operating efficiency of the LSI as
a whole.
10.1
• Four channels
• Four Gbytes of address space in the architecture
• Byte, word, or longword selectable data transfer unit
• 16,777,216 transfers, maximum
• Address mode
• Channel function: Transfer modes that can be set are different for each channel.
• Transfer requests: There are three DMAC transfer activation requests, as indicated below.
• Selectable bus modes: Cycle-steal mode or burst mode
• Two types of DMAC channel priority ranking: Fixed priority mode or round robin mode
• CPU can be interrupted when the specified number of data transfers are complete.
• Module standby mode can be set.
DMASH20A_010020020700
⎯ Dual address mode or single address mode can be selected.
⎯ Direct access or indirect access can be selected in dual address mode.
⎯ Channel 0: Single or dual address mode. External requests are accepted.
⎯ Channel 1: Single or dual address mode. External requests are accepted.
⎯ Channel 2: Dual address mode only. Source address reload function is available.
⎯ Channel 3: Dual address mode only. Direct address transfer mode and indirect address
⎯ External request: From two DREQ pins. DREQ can be detected either by falling edge or by
⎯ Requests from on-chip peripheral modules: Transfer requests from on-chip modules such
⎯ Auto-request: The transfer request is generated automatically within the DMAC.
Section 10 Direct Memory Access Controller (DMAC)
transfer mode selectable.
low level.
as SCI (request made to SCI_0 and SCI_1) or A/D (request made to A/D 1).
Features
10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 167 of 882
REJ09B0108-0400