HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 533

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit Bit Name Initial Value R/W
4
3
AASX
AL
0
0
R/(W)* Second Slave Address Detection Flag
R/(W)* Arbitration Lost Flag
Description
In the I
the first frame after the start condition matches bits SVAX6 to
SVAX0 in SARX.
[Setting condition]
•
[Clearing conditions]
•
•
•
The AL flag indicates that the device, in master mode, has
failed to acquire bus-master status.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Detection of the second slave address in the slave receive
mode while FSX = 0.
Writing of 0 to this bit after reading AASX = 1
Detection of the start condition.
Entering master mode
When the interface is in master transmit mode, the SDA
value it is generating internally and the value on the SDA
pin do not match on the rising edge of SCL.
When the start condition instruction has been executed in
master transmit mode, then the SDA is driven to low by
another device before drives the pin to low.
Writing of data to ICDR (during transmission) or reading of
data from ICDR (during reception).
Writing a 0 to this bit after reading it as 1
2
C bus format in the slave mode, this bit indicates that
Rev.4.00 Mar. 27, 2008 Page 487 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400