HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 136

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Interrupt Controller (INTC)
6.5
Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from the vector numbers and address offsets. In interrupt exception
processing, the exception service routine start address is fetched from the vector table indicated by
the vector table address. For the details of calculation of vector table address, see table 5.4.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and
15 for each pin or module by setting interrupt priority registers A to J (IPRA to IPRJ). However,
the smaller vector number has interrupt source, the higher priority ranking is assigned among two
or more interrupt sources specified by the same IPR, and the priority ranking cannot be changed.
A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module
interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts
from those sources occur simultaneously, they are processed by the default priority order indicated
in table 6.2.
Table 6.2
Rev.4.00 Mar. 27, 2008 Page 90 of 882
REJ09B0108-0400
Interrupt
Source
External pin
User break
H-UDI
—
Interrupts
Interrupt Exception Processing Vectors Table
Interrupt Exception Processing Vectors and Priorities
Name
NMI
Reserved by system 15
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Vector
No.
11
12
14
64
65
66
67
68
69
70
71
Vector Table
Starting Address IPR
H'0000002C
H'00000030
H'00000038
H'0000003C
H'00000100
H'00000104
H'00000108
H'0000010C
H'00000110
H'00000114
H'00000118
H'0000011C
—
—
—
—
IPRA15 to IPRA12
IPRA11 to IPRA8
IPRA7 to IPRA4
IPRA3 to IPRA0
IPRB15 to IPRB12
IPRB11 to IPRB8
IPRB7 to IPRB4
IPRB3 to IPRB0
Default
Priority
High
Low