HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 297

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
7
6
5 to 3 —
2
1
0
Bit Name
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
Initial Value
0
0
All 0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
R/W
Description
Timer Synchronous operation 4 and 3
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit ,
the TCNT clearing source must also be set by means
of bits CCLR0 to CCLR2 in TCR.
0: TCNT_4 and TCNT_3 operate independently
1: TCNT_4 and TCNT_3 performs synchronous
TCNT synchronous presetting/synchronous clearing
is possible
Reserved
These bits are always read as 0. The write value
should always be 0.
Timer Synchronous operation 2 to 0
These bits are used to select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, the TCNT
synchronous presetting of multiple channels, and
synchronous clearing by counter clearing on another
channel, are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit, the
TCNT clearing source must also be set by means of
bits CCLR0 to CCLR2 in TCR.
0: TCNT_2 to TCNT_0 operates independently
1: TCNT_2 to TCNT_0 performs synchronous
TCNT synchronous presetting/synchronous clearing
is possible
(TCNT presetting/clearing is unrelated to other
channels)
operation
(TCNT presetting /clearing is unrelated to other
channels)
operation
11.
Rev.4.00 Mar. 27, 2008 Page 251 of 882
Multi-Function Timer Pulse Unit (MTU)
REJ09B0108-0400