HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 134

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Interrupt Controller (INTC)
6.4.2
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules.
As a different interrupt vector is assigned to each interrupt source, the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers A to J (IPRA to
IPRJ). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits
(I3 to I0) in the status register (SR) to the priority level value of the on-chip peripheral module
interrupt that was accepted.
6.4.3
A user break interrupt has a priority of level 15, and occurs when the break condition set in the
user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are
held until accepted. User break interrupt exception processing sets the interrupt mask level bits (I3
to I0) in the status register (SR) to level 15. For more details on the user break interrupt, see
section 7, User Break Controller (UBC).
Rev.4.00 Mar. 27, 2008 Page 88 of 882
REJ09B0108-0400
IRQ pins
(Acceptance of IRQn interrupt/DTC transfer end/
writing 0 after reading IRQnF = 1)
On-Chip Peripheral Module Interrupts
User Break Interrupt
Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control
detection
detection
RESIRQn
Level
Edge
S
R
Q
IRQnS
IRQnES
ISR.IRQnF
DTC starting request
DTC
CPU interrupt
request