HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 741

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

22.2
Table 22.1 shows the H-UDI pin configuration.
Table 22.1 H-UDI Pins
Pin Name
Test clock
Test mode
select
Test data
input
Test data
output
Test reset
Input/Output Pins
Abbreviation
TCK
TMS
TDI
TDO
TRST
Input
Input
Input
Output
Input
I/O
TCK supplies an independent clock to the H-UDI. As
the clock input to TCK is supplied directly to the H-UDI,
a clock waveform with a duty cycle close to 50%
should be input (see section 26, Electrical
Characteristics, for details).
Test Mode Select Input Signal
TMS is sampled at the rising edge of TCK. TMS
controls the internal state of the TAP controller.
Serial Data Input
TDI performs serial input of instructions and data to H-
UDI registers. TDI is sampled at the rising edge of
TCK.
Serial Data Output
TDO performs serial output of instructions and data
from H-UDI registers. Transfer is synchronized with
TCK. When no signal is being output, TDO goes to the
high-impedance state.
Test Reset Input Signal
TRST is used to initialize the H-UDI asynchronously.
Function
Test Clock Input
Rev.4.00 Mar. 27, 2008 Page 695 of 882
22. User Debugging Interface (H-UDI)
REJ09B0108-0400