HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 571

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 14.7 Examples of Operations in which the DTC Is Used
Item
Slave address +
R/W bit
transmission/recep
tion
Dummy data read ⎯
Main unit data
transmission/recep
tion
Final frame
processing
Setting the
number of frames
of data to be
transferred in DTC
Master Transmit
Mode
DTC transmission
(ICDR write)
DTC transmission
(ICDR write)
Unnecessary
Transmission:
Number of actual
frames of data + 1
(+1 represents the
frame for slave
address + R/W
bits)
CPU reception
Master Receive
Mode
CPU transmission
(ICDR write)
CPU processing
(ICDR read)
DTC reception
(ICDR read)
(ICDR read)
Reception:
Number of actual
frames of data
Rev.4.00 Mar. 27, 2008 Page 525 of 882
Slave Transmit
Mode
CPU reception
(ICDR read)
⎯
DTC transmission
(ICDR write)
Unnecessary
Transmission:
Number of actual
frames of data
14. I
2
C Bus Interface (IIC) Option
Slave Receive
Mode
CPU reception
(ICDR read)
⎯
DTC reception
(ICDR read)
CPU reception
(ICDR read)
Reception:
Number of actual
frames of data
REJ09B0108-0400