HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 520

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14. I
• I
• Synchronous serial format:
14.3.4
ICMR sets the transfer format and transfer rate. ICMR is only accessible when the ICE bit in
ICCR is set to 1.
Rev.4.00 Mar. 27, 2008 Page 474 of 882
REJ09B0108-0400
Bit
7
6
5
4
3
Addressing format with an acknowledge bit
Non-addressing format without an acknowledge bit, and with master operation only
2
C bus format:
2
C Bus Interface (IIC) Option
Bit Name
MLS
WAIT
CKS2
CKS1
CKS0
I
2
C Bus Mode Register (ICMR)
Initial Value
0
0
0
0
0
R/W Description
R/W MSB First/LSB First Select
R/W Wait Insertion
R/W
R/W
R/W
0: MSB first
1: LSB first
When this module is used in the I
should be set to 0.
This bit is enabled only in master mode of the I
format.
0: A wait state is not inserted, and data and the
1: After the clock for the final bit of the data (8th cycle)
For details, refer to section 14.4.7, Timing for Setting
IRIC and the Control of SCL.
Transfer Clock Select 2 to 0
The CKS2 to CKS0 bits, together with the IICX0 bit in
SCRX, select the frequency of the transfer clock. This is
used in the master mode. See table 14.3.
acknowledge bit are transferred consecutively.
become low, the IRIC flag in ICCR is set to 1, and a
wait state is entered (with SCL at the low level).
Clearing the IRIC flag in ICCR to 0 cancels the wait
state. The acknowledge bit is then transferred.
2
C bus format, this bit
2
C bus