HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 1063

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Table A.3
CS6 to CS2, CS0
RD
RD/WR
BS
RAS
CAS
WE0/DQMLL
WE1/DQMLU/WE
WE2/DQMUL/ICIORD
WE3/DQMUU/ICIOWR
CE2A
CE2B
CKE
WAIT
IOIS16
A25 to A0
D7 to D0
D15 to D8
D23 to D16
D31 to D24
Notes: 1. Disabled when the wait setting of the WCR2 register is 0.
2. Unused pins can be switched to port function, pull-up.
Pin
Pin Status (Normal Memory/Little Endian) (cont)
W High
W Low
W Low
W High
W High
W High
R Low
R High
R High
R High
R High
R High
Enabled
Enabled
High
High
High
High
Disabled
Enabled *
Disabled
Address
Valid data Invalid
Invalid
data
Invalid
data
Invalid
data
(Address
Access
Byte
4n)
1
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
Low
High
High
High
High
High
High
Disabled
Enabled *
Disabled
Address
data
Valid data Invalid
Invalid
data
Invalid
data
(Address
Access
4n+1)
Byte
1
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
High
High
Low
High
High
High
High
Disabled
Enabled *
Disabled
Address
Invalid
data
data
Valid data Invalid
Invalid
data
(Address
Access
4n+2)
Byte
32-Bit Bus Width
1
Rev.6.00 Mar. 27 2009 Page 1005 of 1036
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
High
High
High
High
Low
High
High
Disabled
Enabled *
Disabled
Address
Invalid
data
Invalid
data
data
Valid data Invalid
(Address
Access
4n+3)
Byte
1
Enabled
Low
High
High
Low
Enabled
High
High
High
Low
High
Low
High
High
High
High
High
High
Disabled
Enabled *
Disabled
Address
Valid data Invalid
Valid data Invalid
Invalid
data
data
(Address
Access
Word
4n)
Appendix A Pin Functions
1
Enabled
Low
High
High
Low
Enabled
High
High
High
High
High
High
High
Low
High
Low
High
High
Disabled
Enabled *
Disabled
Address
data
data
Valid data Valid data
Valid data Valid data
(Address
Access
REJ09B0254-0600
4n+2)
Word
1
High
High
Longword
Enabled
Low
High
High
Low
Enabled
High
High
High
Low
High
Low
High
Low
High
Low
Disabled
Enabled *
Disabled
Address
Valid data
Valid data
Access
1