HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 266
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
- Current page: 266 of 1098
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Section 8 User Break Controller
Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1, IDA0): Selects the instruction
fetch cycle or data access cycle as the bus cycle of the channel A break condition.
Bit 5: IDA1
0
1
Bits 3 and 2—Read/Write Select A (RWA1, RWA0): Selects the read cycle or write cycle as the
bus cycle of the channel A break condition.
Bit 3: RWA1
0
1
Bits 1 and 0—Operand Size Select A (SZA1, SZA0): Selects the operand size of the bus cycle
for the channel A break condition.
Bit 1: SZA1
0
1
Rev.6.00 Mar. 27, 2009 Page 208 of 1036
REJ09B0254-0600
Bit 4: IDA0
0
1
0
1
Bit 2: RWA0
0
1
0
1
Bit 0: SZA0
0
1
0
1
Description
Condition comparison is not performed
The break condition is the instruction fetch cycle
The break condition is the data access cycle
The break condition is the instruction fetch cycle or data access
cycle
Description
Condition comparison is not performed
The break condition is the read cycle
The break condition is the write cycle
The break condition is the read cycle or write cycle
Description
The break condition does not include operand size
The break condition is byte access
The break condition is word access
The break condition is longword access
(Initial value)
(Initial value)
(Initial value)
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