HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 365

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 15—Area 6 Wait Control (A6W3): The A6W3 bit specifies the number of inserted wait
states for area 6 combined with bits A6W2 to A6W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0 when area 6 is not set to PCMCIA.
A6W3
0
1
Bit 14—Area 5 Wait Control (A5W3): The A5W3 bit specifies the number of inserted wait
states for area 5 combined with bits A5W2 to A5W0 in WCR2. It also specifies the number of
transfer states in burst transfer. Set this bit to 0 when area 5 is not set to PCMCIA.
The relationship between the setting value and the number of waits is the same as A6W3.
Bits 13 and 12—Reserved: These bits are always read as 0. The write value should always be 0.
A6W2
0
1
0
1
A6W1
0
1
0
1
0
1
0
1
A6W0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Inserted
Wait State
(Initial value)
0
1
2
3
4
6
8
10
12
14
18
22
26
30
34
38
Top Cycle
WAIT Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Rev.6.00 Mar. 27, 2009 Page 307 of 1036
Section 12 Bus State Controller (BSC)
Number of
States per
One-data
Transfer
2
2
3
4
5
7
9
11
13
15
19
23
27
31
35
39
Burst Cycle
REJ09B0254-0600
WAIT Pin
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled