HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 51

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 1 Overview and Pin Functions
Table 1.1
Table 1.2
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Table 2.13
Table 2.14
Table 2.15
Table 2.16
Table 2.17
Table 2.18
Table 2.19
Table 2.20
Table 2.21
Table 2.22
Table 2.23
Table 2.24
Table 2.25
Table 2.26
Table 2.27
Table 2.28
Table 2.29
Table 2.30
Table 2.31
Table 2.32
Table 2.33
Table 2.34
SH7727 Features ....................................................................................................
SH7727 Pin Function ............................................................................................. 11
Initial Register Values ............................................................................................ 24
Detail Behavior Under Each SH3-DSP Mode........................................................ 33
Destination Register of DSP Instructions............................................................... 34
Source Register of DSP Operations ....................................................................... 35
DSR Register Bits .................................................................................................. 36
Word Data Sign Extension ..................................................................................... 41
Delayed Branch Instructions .................................................................................. 41
T Bit ....................................................................................................................... 42
Immediate Data Referencing.................................................................................. 42
Absolute Address Referencing ............................................................................... 43
Displacement Referencing ..................................................................................... 43
Addressing Modes and Effective Addresses for CPU Instructions ........................ 44
Overview of Data Transfer Instructions ................................................................. 48
CPU Instruction Formats........................................................................................ 55
Double Data Transfer Instruction Formats ............................................................. 59
Single Data Transfer Instruction Formats .............................................................. 60
A-Field Parallel Data Transfer Instructions............................................................ 61
B-Field ALU Operation Instructions and Multiply Instructions ............................ 62
CPU Instruction Types ........................................................................................... 65
Data Transfer Instructions ...................................................................................... 69
Arithmetic Operation Instructions.......................................................................... 71
Logic Operation Instructions.................................................................................. 73
Shift Instructions .................................................................................................... 74
Branch Instructions ................................................................................................ 75
System Control Instructions ................................................................................... 76
Added CPU System Control Instructions............................................................... 81
Double Data Transfer Instructions ......................................................................... 83
Single Data Transfer Instructions........................................................................... 84
Correspondence between DSP Data Transfer Operands and Registers.................. 85
DSP Operation Instruction Formats ....................................................................... 86
Correspondence between DSP Instruction Operands and Registers....................... 87
DSP Operation Instructions.................................................................................... 88
DC Bit Update Definitions ..................................................................................... 94
Examples of NOPX and NOPY Instruction Codes ................................................ 96
Tables
Rev.6.00 Mar. 27, 2009 Page xlix of lvi
REJ09B0254-0600
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