HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 536

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 16 Realtime Clock (RTC)
16.4
16.4.1
During the RTC count operation (RCR2 bits 0 = 1), the following registers cannot be written.
RSECCNT, RMICNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, and RYRCNT
To write these registers, the RTC count operation should be stopped.
16.4.2
Figure 16.6 shows the periodic interrupt function setting flow.
Periodic interrupts can be generated with the period specified by the periodic interrupt enable flag
(PES) in the RTC control register (RCR2). When the time period specified by PES passed, the
periodic interrupt flag (PEF) is set to 1.
PEF is cleared to 0 when PES is set and a periodic interrupt is generated. The periodic interrupt
generation can be checked by reading this bit, but is usually checked by the interrupt function.
Rev.6.00 Mar. 27, 2009 Page 478 of 1036
REJ09B0254-0600
Usage Notes
Writing Registers During RTC Count Operation
RTC Periodic Interrupts
Figure 16.6 Periodic Interrupt Function Setting
Period set by PES passed
Set PES and clear PEF
Clears PEF
PES is set and PEF is
cleared in RCR2.
PEF is cleared to 0.