HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 700

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
(2) Receiving in Master
Figure 20.10 shows an example of receiving and operation in master.
Rev.6.00 Mar. 27, 2009 Page 642 of 1036
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Settting of SIMDR register,
SISCR register, SITDAR register,
SIRDAR register, SICDAR register,
SIFCTR register
"1" is set to SCKE bit of SICTR register
SCK_SIO begin to transmit
“1” is set to FSE bit of SICTR register
"1" is set to RXE bit of SICTR register
Synchronized to SIOFSYNC receive data
from RxD_SIO is stored to SIRDR
Setting of SIRDR register
"0" is set to RXE bit of SICTR register
Finish to transmit?
RDREQ = 1?
Time chart
Figure 20.10 Example of Receive Operation in Master
Start
End
Y
Y
N
N
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Set the beggin to operation
of baud rate generator
Set the begin to transmit of
frame synchronized signal
Set the transmit enable
Reading of receive data
Set to transmit disable
Setting content of SIOF
Transmit serial clock
Transmit frame
synchronized signal
Receive request is
submitted by limit of
reveive FIFO
Receive
Finish to receive
SIOF operation