HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 307

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

9.5.2
The module standby function can be cleared by clearing the MSTP17, MSTP15 to MSTP13,
MSTP11 to MSTP4, and MSTP2 to MSTP0 bits to 0, or by a power-on reset or manual reset.
9.6
The timing of STATUS1 and STATUS0 pin changes is shown in figures 9.2 to 9.9.
The meanings of STATUS are as follows:
• Reset:
• Sleep:
• Standby: LH (STATUS1 is low, STATUS0 is high)
• Normal: LL (STATUS1 is low, STATUS0 is low)
The meanings of clock units are as follows:
• Bcyc: Bus clock cycle
• Pcyc: Peripheral clock cycle
• Rcyc: 32.768-kHz RTC clock cycle
9.6.1
Power-On Reset
Note: * CKIO2 can be used at only clock modes 0, 1 and 2.
CKIO,
CKIO2*
RESETP
STATUS
Figure 9.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output
Clearing the Module Standby Function
Timing of STATUS Pin Changes
Timing for Resets
HH (STATUS1 is high, STATUS0 is high)
HL (STATUS1 is high, STATUS0 is low)
Normal
0 to 5 Bcyc
PLL settling
time
Section 9 Power-Down Modes and Software Reset
Rev.6.00 Mar. 27, 2009 Page 249 of 1036
Reset
0 to 30 Bcyc
REJ09B0254-0600
Normal