HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 984

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 31 User-Debugging Interface (H-UDI)
31.4.2
Table 31.4 Reset Configuration
ASDMD0 *
H
L
Notes: 1. Performs main chip mode and ASE mode settings
Rev. 5.00 Dec 12, 2005 page 926 of 1034
REJ09B0254-0500
2. During ASE mode, reset hold is enabled by setting RESETP and TRST pins at low level
3. There are two ASE modes, one for executing software in the emulator’s firmware (ASE
Reset Configuration
1
ASEMD0 = H, main chip mode
ASEMD0 = L, ASE mode
When user system is used alone without using emulator or H-UDI, set ASEMD0 to H.
• Boot request from H-UDI (boot sequence)
• Another RESETP assert (power-on reset)
for a constant cycle. In this state, the CPU does not start up, even if RESETP is set to
high level. When TRST is set to high level, H-UDI operation is enabled, but the CPU
does not start up. The reset hold state is cancelled by the following:
break mode) and one for executing user software (ASE user mode).
RESETP
L
H
L
H
TRST
L
H
L
H
L
H
L
H
Chip State
Normal reset and H-UDI reset
Normal reset
H-UDI reset only
Normal operation
Reset hold *
ASE user mode *
ASE break mode *
H-UDI reset only
Normal operation
2
3
: Normal reset
3
: RESETP assertion masked