HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 427

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bits 4 to 2—Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Specifies
the type of memory connected to the physical space areas 2 and 3. Before using LCDC and USB,
set area 3 to synchronous DRAM (DRAMTP2 to DRAMTP0 equal to 010 or 011).
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
1
Notes: 1. It is not possible to access synchronous DRAM if clock ratio Iφ:bus clock = 1:1.
Bits 1 and 0 —Not referenced
2. When selecting this mode, set the same bus width for area 2 and area 3.
0
1
0
1
0
1
0
1
0
1
0
1
Rev.6.00 Mar. 27, 2009 Page 369 of 1036
Section 13 Li Bus State Controller (LBSC)
Ordinary memory for areas 2 and 3
Reserved (Setting disabled)
Ordinary memory for area 2 and
synchronous DRAM for area 3 *
Synchronous DRAM for areas 2 and 3 *
Reserved
Reserved
Reserved (Setting disabled)
Reserved (Setting disabled)
REJ09B0254-0600
(Initial value)
1
1
*
2