HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 1093

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

The port G control register (PGCR) is a readable and writeable 16-bit register used to select pin
functions. PGCR is initialized to H'AAAA (ASEMD0 = 1) or H'A200 (ASEMD0 = 0) at power-on
reset, but it is not initialized by manual resets or in the standby mode or sleep mode.
Bits 15, 14: PG7 Mode 1, 0 (PG7MD1, PG7MD0)
Bits 13, 12: Reserved
Bits 11, 10: PG5 Mode 1, 0 (PG5MD1, PG5MD0)
Bits 9, 8: PG4 Mode 1, 0 (PG4MD1, PG4MD0)
Bits 7, 6: PG3 Mode 1, 0 (PG3MD1, PG3MD0)
Bits 5, 4: PG2 Mode 1, 0 (PG2MD1, PG2MD0)
Bits 3, 2: PG1 Mode 1, 0 (PG1MD1, PG1MD0)
Bit 1: Reserved
Bits 3, 0: PG0 Mode 1, 0 (PG1MD1, PG0MD0)
These bits are used to select pin functions and input pull-up MOS control settings. In the PG1 and
PG0 modes, bit 3 (PG1MD1) is used to select between “other function” and “port input.” When
the port input setting is selected (PG1MD1 = 1), pull-up MOS on-off selection is performed using
bit 2 (PG1MD0) in the PG1 mode and bit 0 (PG0MD0) in the PG0 mode.
Initial value:
Initial value:
Appendix F Using Port G Control Register (PGCR) with
Appendix F Using Port G Control Register (PGCR) with Versions Previous to the SH7727C
R/W:
R/W:
Bit:
Bit:
PG7MD1 PG7MD0
PG3MD1 PG3MD0 PG2MD1 PG2MD0 PG1MD1 PG1MD0
R/W
R/W
1/0
15
1
7
Versions Previous to the SH7727C
R/W
R/W
14
0
6
0
R/W
1/0
13
—
R
1
5
R/W
12
—
R
0
4
0
Rev.6.00 Mar. 27, 2009 Page 1035 of 1036
PG5MD1 PG5MD0 PG4MD1 PG4MD0
R/W
R/W
1/0
1/0
11
3
R/W
R/W
10
0
2
0
REJ09B0254-0600
R/W
1/0
—
R
9
1
1
PG0MD0
R/W
R/W
8
0
0
0