HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 281

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

3. When the condition is specified to be occurred after execution, the instruction set with the
4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored.
8.3.3
1. The memory cycles in which CPU data access breaks occur are from instructions.
2. The relationship between the data access cycle address and the comparison condition for
Table 8.2
Access Size
Longword
Word
Byte
3. When the data value is included in the break conditions on B channel:
4. When the DMAC data access is included in the break condition:
break condition is executed and then the break is generated prior to the execution of the next
instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions.
When this kind of break is set for a delay branch instruction, the break is generated at the
instruction that then first accepts the break.
There is thus no need to set break data for the break of the instruction fetch cycle.
operand size are listed in table 8.2:
This means that when address H'00001003 is set without specifying the size condition, for
example, the bus cycle in which the break condition is satisfied is as follows (where other
conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
When the data value is included in the break conditions, either longword, word, or byte is
specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data
values are included in break conditions, a break is generated when the address conditions and
data conditions both match. To specify byte data for this case, set the same data in two bytes at
bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B
(BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored.
When the address is included in the break condition on DMAC data access, the operand size of
the break bus cycle registers (BBRA and BBRB) should be byte, word or no operand size
specification. When the data value is included, select either byte or word.
Break by Data Access Cycle
Data Access Cycle Addresses and Operand Size Comparison Conditions
Address Compared
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Compares break address register bits 31 to 0 to address bus bits 31 to 0
Rev.6.00 Mar. 27, 2009 Page 223 of 1036
Section 8 User Break Controller
REJ09B0254-0600