HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 550

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 17 Serial Communication Interface (SCI)
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt
(TXI) requested when the transmit data register empty bit (TDRE) in the serial status register
(SCSSR) is set to 1 due to transfer of serial transmit data from the SCTDR to the SCTSR.
Bit 7: TIE
0
1
Note: * The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the receive data register full bit (RDRF) in the serial status register (SCSSR) is set
to 1 due to transfer of serial receive data from the SCRSR to the SCRDR. It also enables or
disables receive-error interrupt (ERI) requests.
Bit 6: RIE
0
1
Note: * RXI and ERI interrupt requests can be cleared by reading the RDRF flag or error flag
Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE
0
1
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SCSSR) is
Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Rev.6.00 Mar. 27, 2009 Page 492 of 1036
REJ09B0254-0600
2. Serial transmission starts when the transmit data register empty (TDRE) bit in the serial
clearing TDRE to 0, or by clearing TIE to 0.
(FER, PER, or ORER) after it has been set to 1, then clearing the flag to 0, or by clearing
RIE to 0.
fixed to 1.
status register (SCSSR) is cleared to 0 after writing of transmit data into the SCTDR.
Select the transmit format in the SCSMR before setting TE to 1.
Description
Transmit-data-empty interrupt request (TXI) is disabled*
Transmit-data-empty interrupt request (TXI) is enabled
Description
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
disabled*
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
enabled
Description
Transmitter disabled *
Transmitter enabled *
2
1
(Initial value)
(Initial value)
(Initial value).