HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 149
![SH3-DSP, LEAD FREE](/photos/28/62/286203/240-bfqfp__prqp0240kc-b_sml.jpg)
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
- Current page: 149 of 1098
- Download datasheet (7Mb)
Instruction
DCT
DCT
DCF
DCF
DCT POR Sx,Sy,Dz
DCF POR Sx,Sy,Dz
DCT PAND Sx,Sy,Dz
DCF PAND Sx,Sy,Dz
DCT PXOR Sx,Sy,Dz
DCF PXOR Sx,Sy,Dz
PAND Sx,Sy,Dz
PXOR Sx,Sy,Dz
PDEC Sx,Dz
PDEC Sy,Dz
PNEG Sx,Dz
PNEG Sy,Dz
PNEG Sx,Dz
PNEG Sy,Dz
POR Sx,Sy,Dz 111110**********
Instruction Code
111110**********
11001010xx00zzzz
111110**********
1110101000yyzzzz
111110**********
11001011xx00zzzz
111110**********
1110101100yyzzzz
10110101xxyyzzzz
111110**********
10110110xxyyzzzz
111110**********
10110111xxyyzzzz
111110**********
10010101xxyyzzzz
111110**********
10010110xxyyzzzz
111110**********
10010111xxyyzzzz
111110**********
10100101xxyyzzzz
111110**********
10100110xxyyzzzz
111110**********
10100111xxyyzzzz
111110**********
10001001xx00zzzz
111110**********
1010100100yyzzzz
If DC = 1, 0 – Sx → Dz
If DC = 0, nop
If DC = 1, 0 – Sy → Dz
If DC = 0, nop
If DC = 0, 0 – Sx → Dz
If DC = 1, nop
If DC = 0, 0 – Sy → Dz
If DC = 1, nop
Sx | Sy → Dz
If DC = 1, Sx | Sy → Dz
If DC = 0, nop
If DC = 0, Sx | Sy → Dz
If DC = 1, nop
Sx & Sy → Dz
If DC = 1, Sx & Sy → Dz
If DC = 0, nop
If DC = 0, Sx & Sy → Dz
If DC = 1, nop
Sx ^ Sy → Dz
If DC = 1, Sx ^ Sy → Dz
If DC = 0, nop
If DC = 1, Sx ^ Sy → Dz
If DC = 0, nop
Sx [39:16] – 1 → Dz
Sy [31:16] – 1 → Dz
Operation
Rev.6.00 Mar. 27, 2009 Page 91 of 1036
REJ09B0254-0600
Execu-
tion
States
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Section 2 CPU
DC
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
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