HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 86

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 2 CPU
three-step instruction. When RF[1:0] = 10, it means the current repeat module consists of four or
more instructions.
Although RC[11:0] and RF[1:0] can be changed by a store/load to SR, use of the dedicated
manipulation instruction SETRC is recommended.
The SR also has a 12-bit repeat counter RC which is used for efficient loop control. Repeat start
register (RS) and repeat end register (RE) are also introduced for the loop control. They keep the
start and end addresses of a loop (the contents of the registers, RS and RE are slightly different
from the actual loop start and end address).
Modulo register, MOD is introduced to realize modulo addressing for circular data buffering.
MOD keeps the modulo start address (MS) and the modulo end address (ME).
In order to access RS, RE and MOD, load/store (control register) instructions for them are
introduced. An example for RS is as follows:
Address set instructions for the RS and RE are also prepared.
Rev.6.00 Mar. 27, 2009 Page 28 of 1036
REJ09B0254-0600
LDC Rm,RS;
LDC.L @Rm+,RS;
STC RS,Rn;
STC.L RS,@-Rn;
LDRS @(disp,PC); disp × 2 + PC → RS
LDRE @(disp,PC); disp × 2 + PC → RE
Rm → RS
(Rm) → RS, Rm+4 → Rm
RS → Rn
Rn-4 → Rn, RS → (Rn)