HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 802
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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Section 24 USB HOST Module
24.2.15 HcFmRemaining
HcFrameRemaining Register (H'04000438)
The HcFmRemaining register is a 14-bit down counter indicating the bit time remaining in the
current frame.
Register: HcFrameRemaining
Bits
31
30–14
13–0
Rev.6.00 Mar. 27, 2009 Page 744 of 1036
REJ09B0254-0600
Reset
0b
0h
0b
R/W
R
—
R
Offset: 38–3B
Description
FrameRemainingToggle (FRT)
This bit is always loaded from the FrameIntervalToggle bit in
HcFminterval when FrameReamining reaches 0. This bit is used
by HCD for the synchronization between FrameInterval and
FrameReamining.
Reserved.
FrameRemaining (FR)
This counter is decremented at each bit time. When this counter
reaches 0, this counter is reset by loading the value of the
FramInterval bit specified in the HcFminterval register at the
next bit time boundary. When the host controller transits to the
UsbOperational state, it read the FrameInterval bit in the
HcFminterval register again and use the updated value from the
next SOF.
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