HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 710

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 20 Serial IO (SIOF)
20.4
Note the following when using the SIOF.
For details on using versions previous to the SH7727B please refer to 20.4.1, Notes on Using the
SIOF with Versions Previous to the SH7727B, in addition to the notes below.
1. Using the transmit function in sleep mode
2. Using control data transmission/reception consecutively on control data interface (secondary
3. DMA transfer
4. Access from the CPU
5. Transmit/receive FIFO underflow
Rev.6.00 Mar. 27, 2009 Page 652 of 1036
REJ09B0254-0600
If transmission is enabled when data has already been written to the transmit FIFO, one or two
of the initial data bytes may be lost.
Therefore, data should not be written to the transmit FIFO before enabling transmission.
FS position)
The TCRDY value may become 1 before transmit control data is sent, and if the next control
data is written to the control data register at this point, the control data waiting to be sent will
be overwritten and erased.
At this time, also, the control sequence is disrupted and the SIOF switches around the primary
FS and secondary FS, with the result that transmission/reception of data and control data can
no longer be performed normally.
The control data register should therefore be written to after transmit control data has been
sent.
Example:
Reference RCRDY, and write to the control data register when RCRDY is 1.
After transmit control data has been written, it is essential to read the receive control register
(SIRCR) and clear RCRDY.
Do not use 16-byte DMA transfer. (See section 14.3.4, DMA Transfer Types.)
When performing access from the CPU, do not access the SIOF's transmit/receive FIFO
consecutively, but instead insert an access to somewhere else between SIOF transmit/receive
FIFO accesses.
If the transmit/receive FIFO underflows during a transmit/receive operation, control of the
SIOF's transmit/receive FIFO may fail and data may be lost.
To prevent this, either set a watermark so that underflow does not occur, or execute a transmit
reset (TXRST) or receive reset (RXRST) when an empty interrupt is generated.
Usage Notes