HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 61

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Item
DSP
Clock pulse
generator (CPG)
Features
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Mixture of 16-bit and 32-bit instructions
32-/40-bit internal data bus
Multiplier, ALU, barrel shifter and DSP register
16 bits x 16 bits → 32-bit one cycle multiplier
Large DSP data register
⎯ Six 32-bit data registers
⎯ Two 40-bit data registers
Extended Harvard Architecture for DSP data bus
⎯ Two data buses
⎯ One instruction bus
Max. four parallel operations: ALU, multiply and two load or store
Two addressing units to generate addresses for two memory access
DSP data addressing modes: increment, indexing (with or without modulo
addressing)
Zero overhead repeat loop control
Conditional execution instructions
User-DSP mode and privileged-DSP mode
Clock mode: An input clock can be selected from the external input (EXTAL
or CKIO) or crystal resonator.
Three types of clocks generated:
⎯ CPU clock: 1–16 times the input clock
⎯ Bus clock: 1–4 times the input clock
⎯ Peripheral clock: 1/4–4 times the input clock
Power-down modes:
⎯ Sleep mode
⎯ Standby mode
⎯ Module standby mode (X/Y memory standby enabled)
One-channel watchdog timer
Rev.6.00 Mar. 27, 2009 Page 3 of 1036
Section 1 Overview and Pin Functions
REJ09B0254-0600