HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 457

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Notes: 1. In auto-request mode, transfer begins when AE, NMIF and TE are all 0 and the DE and
(SAR, DAR, DMATCR, CHCR, DMAOR)
DMATCRD1 → DMATCR, SAR and DAR
DEI interrupt request (when IE = 1)
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst
DME bits are set to 1.
mode.
AE = 1 or NMIF = 1 or
AE, NMIF, TE = 0?
Transfer (1 transfer unit);
DE, DME = 1 and
Transfer request
DE = 0 or DME
DMATCR = 0?
Initial settings
Yes
Transfer end
Yes
Yes
Yes
occurs?
Start
Does
= 0?
updated
*1
Figure 14.2 DMAC Transfer Flowchart
No
No
No
No
Section 14 Direct Memory Access Controller (DMAC)
AE = 1 or NMIF = 1 or
Transfer aborted
DE = 0 or DME
Normal end
Yes
*3
Rev.6.00 Mar. 27, 2009 Page 399 of 1036
Does
= 0?
DREQ detection selection
transfer request mode,
Bus mode,
system
No
*2
REJ09B0254-0600