HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 915

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
28.1
This LSI includes a 10-bit successive-approximation A/D converter with a selection of up to six
analog input channels.
28.1.1
A/D converter features are listed below.
• 10-bit resolution
• Six input channels
• High-speed conversion
• Three conversion modes
• Four 16-bit data registers
• Sample-and-hold function
• A/D conversion can be externally triggered
• A/D interrupt requested at the end of conversion
⎯ Conversion time: maximum 15 µs per channel (with 33-MHz peripheral clock)
⎯ Single mode: A/D conversion of one channel
⎯ Multi mode: A/D conversion on one to four channels
⎯ Scan mode: Continuous A/D conversion on one to four channels
⎯ A/D conversion results are transferred for storage into data registers corresponding to the
⎯ At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
channels.
Overview
Features
Section 28 A/D Converter
Rev.6.00 Mar. 27, 2009 Page 857 of 1036
Section 28 A/D Converter
REJ09B0254-0600

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