HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 765

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

(1) Setup Stage
Notes: 1. The application analyzes command data from the host that must be processed by the application in
(USBIFR0/SETUP TS = 1)
Receive 8-byte command
SETUP token reception
2. When the transfer direction is control-out, enable an EP0i transfer request interrupt that is required
Set receive-end flag
of setup command
be processed by
the setup stage, and decides the following processing methods (for instance, data stage direction).
in the status stage. When the transfer direction is control-in, disable the interrupt since it is not
used.
To data stage
Command to
data in EP0s
application?
USB function
Yes
Figure 23.5 Setup Stage Operation
No
Interrupt request
processing by
this module
Automatic
Rev.6.00 Mar. 27, 2009 Page 707 of 1036
Clear EP0o FIFO (USBFCLR/EP0oCLR = 1)
Clear EP0i FIFO (USBFCLR/EP0iCLR = 1)
To control-in
data stage
Section 23 USB Function Controller
Decide data stage direction
Read 8-byte data from EP0s
Write 1 to EP0s read-end bit
(USBTRG/EP0s RDFN = 1)
(USBIFR0/SETUP TS = 0)
Decode command data
Clear SETUP TS flag
Application
*2
REJ09B0254-0600
To control-out
data stage
*1