HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 216

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 5 Cache
In the address field, specify the entry address selecting the entry (bits 11 to 4), W for selecting the
way (bits 12 and 11: in normal mode (8-kbyte cache), 00 is way 0, 01 is way 1, 10 is way 2, and
11 is way 3), and H'F0 to indicate address array access (bits 31 to 24).
When writing, specify bit 3 as the A bit. The A bit indicates whether addresses are compared
during writing. When the A bit is 1, the addresses of four entries selected by the entry addresses
are compared to the addresses to be written into the address array specified in the data field.
Writing takes place to the way that has a hit. When a miss occurs, nothing is written to the address
array and no operation occurs. The way number (W) specified in bits 12 and 11 is not used. When
the A bit is 0, it is written to the entry selected with the entry address and way number without
comparing addresses. The address specified by bits 31 to 10 in the data specification in figure 5.6
(1), address array access, is a logical address. When the MMU is enabled, the address is translated
into a physical address, then the physical address is used in comparing addresses when the A bit is
1. The physical address is written into the address array.
When reading, the address tag, V bit, U bit, and LRU bits of the entry specified by the entry
address and way number (W) are read using the data format shown in figure 5.6 without
comparing addresses. To invalidate a specific entry, specify the entry by its entry address and way
number, and write 0 to its V bit. To invalidate only an entry for an address to be invalidated,
specify 1 for the A bit.
When an entry for which 0 is written to the V bit has a U bit set to 1, it will be written back. This
allows coherency to be achieved between the external memory and cache by invalidating the
entry. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry.
In the SH7727, the upper 3 bits of the 32-bit physical address are treated as a shadow field (see
section 12, Bus State Controller (BSC)). Therefore, when a cache miss occurs, 0 is stored in the
upper 3 bits of the address array address tag.
When using an MOV instruction to modify the address array directly, a nonzero value must not be
written to the upper 3 bits of the address tag.
5.4.2
Data Array
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array ((2) in figure 5.6).
Rev.6.00 Mar. 27, 2009 Page 158 of 1036
REJ09B0254-0600