HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 83

SH3-DSP, LEAD FREE

HD6417727F100CV

Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet

Specifications of HD6417727F100CV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
2.1.1
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are
used for data processing and address calculation.
With SuperH microcomputer type instructions, R0 is used as an index register. With a number of
instructions, R0 is the only register that can be used. R15 is used as the stack pointer (SP). In
exception handling, R15 is used to reference the stack when saving and restoring the status register
(SR) and program counter (PC).
With DSP type instructions, eight of the sixteen general registers are used for addressing of X and
Y data memory and data memory (single data) that uses the L-bus.
To access X memory, R4 and R5 are used as X address register [Ax] and R8 is used as X index
register [Ix]. To access Y memory, R6 and R7 are used as Y address register [Ay] and R9 is used
as Y index register [Iy]. To access single data that uses the L-bus, R2, R3, R4, and R5 are used as
single data address register [As] and R8 is used as single data index register [Is].
Figure 2.3 shows the general purpose registers, which are identical to SH-3’s, when DSP
extension is disabled.
31
General Purpose Registers
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Figure 2.3 General Purpose Register (Not in DSP Mode)
*1 *2
*2
*2
*2
*2
*2
*2
*2
0
General Registers (when not in DSP mode)
Notes: 1. R0 functions as an index register in the
2. R0 to R7 are banked registers. In user mode,
indexed register-indirect addressing mode
and indexed GBR-indirect addressing mode.
In some instructions, only R0 can be used as
the source register or destination register.
BANK0 is used. In privileged mode, SR.RB
specifies BANK.
SR.RB = 0; BANK0 is used
SR.RB = 1; BANK1 is used
Rev.6.00 Mar. 27, 2009 Page 25 of 1036
REJ09B0254-0600
Section 2 CPU

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