HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 725

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 0—RX FIFO Half Size Full (RHF)
Bit 0: RHF
0
1
Set condition:
1. The half of specified size with FFSZ (ACTR1) of receive data is accumulated into FIFO.
Clear condition:
1. Reset
2. Number of data in FIFO becomes smaller than the half of the size that is indicated by FFSZ
3. RE bit (ACTR1) is set to 0
(2) AFEIF Status Register 2 (ASTR2)
ASTR2 is the register that is composed of interrupt status flag (2 bits) relating DAA control and
mask flag (2 bits) of interrupt signals for DAA control. Status flags shows statuses of ringing
detect interrupt, end of dial pulse output interrupt. Interrupt flags are cleared by 0 write after read
action of this register. Each Interrupt signal are able to be masked by each interrupt masks.
Bit 9—Dial Pulse End Interrupt Mask (DPEM)
Bit 9: DPEM
0
1
Initial value:
Initial value:
(ACTR1).
R/W:
R/W:
Bit:
Bit:
15
—
—
R
R
0
7
0
Description
Normal state
Rx FIFO half size interrupt
Description
Interrupt enable
Interrupt mask
14
—
—
R
R
0
6
0
13
—
—
R
R
0
5
0
12
—
—
R
R
Section 21 Analog Front End Interface (AFEIF)
0
4
0
Rev.6.00 Mar. 27, 2009 Page 667 of 1036
11
—
—
R
R
0
3
0
10
—
—
R
R
0
2
0
DPEM
REJ09B0254-0600
DPE
R/W
R/W
9
1
1
0
(Initial value)
(Initial value)
RDETM
RDET
R/W
R/W
8
1
0
0