HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 369
HD6417727F100CV
Manufacturer Part Number
HD6417727F100CV
Description
SH3-DSP, LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417727BP100CV.pdf
(1098 pages)
Specifications of HD6417727F100CV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
100MHz
Connectivity
FIFO, SCI, SIO, SmartCard, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 2.05 V
Data Converters
A/D 6x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
240-QFP Exposed Pad, 240-eQFP, 240-HQFP
Cpu Family
SuperH
Device Core Size
32b
Frequency (max)
100MHz
Interface Type
SCI/USB
Program Memory Size
Not Required
Total Internal Ram Size
16KB
# I/os (max)
104
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2.05/3.6V
Operating Supply Voltage (min)
1.6/2.6V
On-chip Adc
6-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
RISC
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant
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12.2.8
The refresh timer control/status register (RTCSR) is a 16-bit read/write register that specifies the
refresh cycle, whether to generate an interrupt, and that interrupt's cycle. It is initialized to H'0000
by a power-on reset, but is not initialized by a manual reset or standby mode. Before specifying
the CKS2 to CKS0 of RTCST, the RTCOR must be specified.
Note: Writing to the RTCSR differs from that to general registers to ensure the RTCSR is not
Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Compare Match Flag (CMF): The CMF status flag indicates that the values of RTCNT
and RTCOR match.
Bit 7: CMF
0
1
Note: * Contents do not change when 1 is written to CMF.
Bit 6—Compare Match Interrupt Enable (CMIE): Enables or disables an interrupt request
caused when the CMF of RTCSR is set to 1. Do not set this bit to 1 when using CAS-before-RAS
refresh or auto-refresh.
Bit 6: CMIE
0
1
Initial value:
R/W:
rewritten incorrectly. Use the word-transfer instruction to set the upper byte as
B'10100101 and the lower byte as the write data. For details, see section 12.2.12, Cautions
on Accessing Refresh Control Related Registers.
Bit:
Refresh Timer Control/Status Register (RTCSR)
15
—
R
0
14
—
R
0
Description
The values of RTCNT and RTCOR do not match.
Clear condition: When a refresh is performed After 0 has been written in
CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh).
The values of RTCNT and RTCOR match.
Set condition: RTCNT = RTCOR*
Description
Disables an interrupt request caused by CMF
Enables an interrupt request caused by CMF
13
—
R
0
12
—
R
0
11
—
R
0
10
—
R
0
—
R
9
0
—
R
8
0
Rev.6.00 Mar. 27, 2009 Page 311 of 1036
CMF CMIE CKS2 CKS1 CKS0 OVF OVIE LMTS
R/W
7
0
Section 12 Bus State Controller (BSC)
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
REJ09B0254-0600
R/W
2
0
(Initial value)
(Initial value)
R/W
1
0
R/W
0
0
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