HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 620

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 18 Smart Card Interface
The receive margin is found from the following equation:
For smart card mode:
Where: M = Receive margin (%)
Using this equation, the receive margin when F = 0 and D = 0.5 is as follows:
Rev.6.00 Mar. 27, 2009 Page 562 of 1036
REJ09B0254-0600
data (RxD0)
Base clock
Synchro-
sampling
sampling
Receive
nization
M = (0.5 −
N = Ratio of bit rate to clock (N = 372)
D = Clock duty (D = 0 to 1.0)
L = Frame length (L = 10)
F = Absolute value of clock frequency deviation
M = (0.5 – 1/2 × 372) × 100% = 49.866%
timing
timing
Data
Figure 18.8 Receive Data Sampling Timing in Smart Card Mode
0
186 clock cycles
2N
1
) −
372 clock cycles
(L − 0.5)F −
Start
bit
185
D − 0.5
N
371 0
(1 + F) × 100%
D0
185
371 0
D1