HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 489

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

14.4
14.4.1
The DMAC has an on-chip compare-match timer (CMT) to generate DMA transfer requests. The
CMT is 16-bit counter.
Features
The CMT has the following features:
• Four types of counter input clocks can be selected
• Generates a DMA transfer request when a compare-match occurs.
Block Diagram
Figure 14.26 shows a CMT block diagram.
CMCOR0:
CMCSR0:
⎯ One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, and Pφ/64) can be selected.
CMCNT0:
CMSTR:
Compare-Match Timer (CMT)
Overview
Compare match timer start register
Compare match timer control/status register 0
Compare match timer constant register 0
Compare match timer counter 0
Control circuit
Figure 14.26 CMT Block Diagram
Pφ/4 Pφ/8 Pφ/16 Pφ/64
Module bus
Clock selection
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 431 of 1036
Internal bus
interface
REJ09B0254-0600
Bus
CMT