HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 451

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bit 1—Transfer End (TE): TE is set to 1 when data transfer ends by the count specified in
DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
Before this bit is set to 1, if data transfer ends due to an NMI interrupt, a DMAC address error, or
clearing the DE bit or the DME bit in DMAOR, this bit is not set to 1. Even if the DE bit is set to
1 while this bit is set to 1, transfer is not enabled.
Bit 1: TE
0
1
Bit 0—DMAC Enable (DE): DE enables channel operation.
Bit 0: DE
0
1
If the auto request is specified in RS3 to RS0, transfer starts when this bit is set to 1. For an
external request or an on-chip module request, transfer starts if a transfer request is generated after
this bit is set to 1. Clearing this bit during transfer can terminate transfer.
Even if the DE bit is set, transfer is not enabled when the TE bit is 1, the DME bit in DMAOR is
0, or the NMIF bit or AE bit in DMAOR is 1.
Description
Data transfer does not end by the count specified in DMATCR
Clear condition: Writing 0 after TE = 1 read at power-on reset or manual reset
Data transfer ends by the specified count
Description
Disables channel operation
Enables channel operation
Section 14 Direct Memory Access Controller (DMAC)
Rev.6.00 Mar. 27, 2009 Page 393 of 1036
REJ09B0254-0600
(Initial value)
(Initial value)