HD6417727F100CV Renesas Electronics America, HD6417727F100CV Datasheet - Page 304

• Manufacturer Part Number: HD6417727F100CV
• Description: SH3-DSP, LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417727F100CV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: FIFO, SCI, SIO, SmartCard, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2.05 V
• Data Converters: A/D 6x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 240-QFP Exposed Pad, 240-eQFP, 240-HQFP
• Cpu Family: SuperH
• Device Core Size: 32b
• Frequency (max): 100MHz
• Interface Type: SCI/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 104
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 2.05/3.6V
• Operating Supply Voltage (min): 1.6/2.6V
• On-chip Adc: 6-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Section 9 Power-Down Modes and Software Reset
Canceling with a Reset: Standby mode can be canceled with a reset (power-on or manual).
Keep the RESET or RESETM pin low until the clock oscillation settles.
The internal clock will be output continuously to the CKIO pin.
9.4.3
In standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the
frequency can be changed. This function is used as follows:
1. Enter standby mode using the procedure for changing to standby mode.
2. When the chip enters standby mode and the clock stopped within the chip, the STATUS1 pin
3. When the STATUS1 pin goes low and the STATUS0 pin goes high, the input clock is stopped
4. When the frequency is changed, an NMI, IRL, IRQ, PINT or on-chip supporting module
5. After the time set in the WDT has elapsed, the clock starts being applied within the chip, the
Rev.6.00 Mar. 27, 2009 Page 246 of 1036
REJ09B0254-0600
WTCNT value
H'FF
H'80
output is low and the STATUS0 pin output is high.
or the frequency is changed.
(except the internal timer) interrupt is input after changing the frequency. When the clock is
stopped, the same interrupts are input after the clock is applied.
STATUS1 and STATUS0 pins both go low, operation resumes from the interrupt exception
handling.
Clock Pause Function
Figure 9.1 Canceling Standby Mode with STBCR.STBY
Interrupt
request
Crystal oscillator settling
time and PLL synchronization
time
WDT overflow and branch to
interrupt handling routine
Clear bit STBCR.STBY before
WTCNT reaches H'80. When
STBCR.STBY is cleared, WTCNT
halts automatically.
Time