NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 122

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Peripheral Reset Control Register1 (IPRSTC1)
Register
IPRSTC1
Bits
[31:4]
[3]
[2]
[1]
[0]
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
EBI_RST
PDMA_RST
CPU_RST
CHIP_RST
Offset
GCR_BA+0x08
30
22
14
6
Reserved
R/W
R/W
Reserved
EBI Controller Reset (Low Density 64 pin package Only) (write-protection bit in
NUC100/NUC120/NUC130/NUC140 Low Density 64-pin package)
Set this bit to 1 will generate a reset signal to the EBI. User need to set this bit to 0 to
release from the reset state.
This bit is the protected bit, It means programming this bit needs to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100
1 = EBI controller reset
0 = EBI controller normal operation
PDMA Controller Reset (write-protection bit in NUC100/NUC120/NUC130/NUC140
Low Density)
Setting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to
0 to release from reset state.
This bit is the protected bit, It means programming this bit needs to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100.
1 = PDMA controller reset
0 = PDMA controller normal operation
CPU kernel one shot reset (write-protection bit)
Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and
this bit will automatically return to 0 after the 2 clock cycles
This bit is the protected bit, It means programming this bit needs to write “59h”, “16h”,
“88h” to address 0x5000_0100 to disable register protection. Reference the register
REGWRPROT at address GCR_BA+0x100
1 = CPU one shot reset
0 = CPU normal operation
CHIP one shot reset (write-protection bit)
29
21
13
5
Description
IP Reset Control Register 1
28
20
12
4
- 122 -
Reserved
Reserved
Reserved
EBI_RST
27
19
11
3
Publication Release Date: Dec. 22, 2010
PDMA_RST
26
18
10
2
CPU_RST
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
CHIP_RST
24
16
8
0