NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 521

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

[20:19]
[18:8]
[7:6]
[5:4]
[3:2]
[1]
[0]
NuMicro™ NUC100 Series Technical Reference Manual
APB_TWS
Reserved
DAD_SEL
SAD_SEL
MODE_SEL
SW_RST
PDMACEN
Peripheral transfer Width Select
00 = One word (32 bits) is transferred for every PDMA operation.
01 = One byte (8 bits) is transferred for every PDMA operation.
10 = One half-word (16 bits) is transferred for every PDMA operation.
11 = Reserved.
Note: This field is meaningful only when MODE_SEL is IP to Memory mode (APB-to-
Memory) or Memory to IP mode (Memory-to-APB).
Reserved
Transfer Destination Address Direction Select
00 = Transfer Destination address is increasing successively.
01 = Reserved.
10 = Transfer Destination address is fixed (This feature can be used when data where
11 = Reserved.
Transfer Source Address Direction Select
00 = Transfer Source address is increasing successively.
01 = Reserved.
10 = Transfer Source address is fixed (This feature can be used when data where
11 = Reserved.
PDMA Mode Select
00 = Memory to Memory mode (Memory-to-Memory).
01 = IP to Memory mode (APB-to-Memory).
10 = Memory to IP mode (Memory-to-APB).
Software Engine Reset
0 = Writing 0 to this bit has no effect.
1 = Writing 1 to this bit will reset the internal state machine, pointers and internal buffer.
PDMA Channel Enable
Setting this bit to 1 enables PDMA’s operation. If this bit is cleared, PDMA will ignore
all PDMA request and force Bus Master into IDLE state.
Note: SW_RST(PDMA_CSRx[1], x= 0~8) will clear this bit
The contents of control register will not be cleared. This bit will auto clear after few
clock cycles.
transferred from multiple sources to a single destination).
transferred from a single source to multiple destinations).
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Publication Release Date: Oct 22, 2010
Revision V1.06