NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 520

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.18.6 Register Description
PDMA Control and Status Register (PDMA_CSRx)
Register
PDMA_CSR0
PDMA_CSR1
PDMA_CSR2
PDMA_CSR3
PDMA_CSR4
PDMA_CSR5
PDMA_CSR6
PDMA_CSR7
PDMA_CSR8
Notice: Low Density only support PDMA channel 0.
Bits
[31:24]
[23]
[22:21]
TRIG_EN
31
23
15
7
DAD_SEL
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
TRIG_EN
Reserved
Offset
PDMA_BA_ch0+0x00
PDMA_BA_ch1+0x00
PDMA_BA_ch2+0x00
PDMA_BA_ch3+0x00
PDMA_BA_ch4+0x00
PDMA_BA_ch5+0x00
PDMA_BA_ch6+0x00
PDMA_BA_ch7+0x00
PDMA_BA_ch8+0x00
30
22
14
6
Reserved
Reserved
TRIG_EN
1 = Enable PDMA data read or write transfer.
0 = No effect.
Note: When PDMA transfer completed, this bit will be cleared automatically.
If the bus error occurs, all PDMA transfer will be stopped. Software must reset all
PDMA channel, and then trigger again.
Reserved
29
21
13
5
SAD_SEL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
PDMA Control and Status Register CH0
PDMA Control and Status Register CH1
PDMA Control and Status Register CH2
PDMA Control and Status Register CH3
PDMA Control and Status Register CH4
PDMA Control and Status Register CH5
PDMA Control and Status Register CH6
PDMA Control and Status Register CH7
PDMA Control and Status Register CH8
28
20
12
4
- 520 -
APB_TWS
Reserved
Reserved
27
19
11
3
MODE_SEL
Publication Release Date: Dec. 22, 2010
26
18
10
2
Reserved
SW_RST
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PDMACEN
24
16
8
0