NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 197

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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NuMicro™ NUC100 Series Technical Reference Manual
PD_WU_STS
PD_WU_INT_EN
PD_WU_DLY
OSC10K_EN
OSC22M_EN
XTL32K_EN
XTL12M_EN
1 = Chip enter the power down mode instant or wait CPU sleep command WFI
0 = Chip operate in normal mode or CPU in idle mode (sleep mode) because of WFI
Power down mode wake up interrupt status
Set by “power down wake up event”, it indicates that resume from power down mode”
The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD or RTC wakeup
occurred
Write 1 to clear the bit to zero.
Power down mode wake up interrupt enable (write-protection bit)
0 = Disable
1 = Enable
The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
Enable the wake up delay counter (write-protection bit)
When the chip wakes up from power down mode, the clock control will delay certain
clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz
crystal, and 256 clock cycles when chip work at internal 22.1184 MHz oscillator.
1 = Enable clock cycles delay
0 = Disable clock cycles delay
Internal 10 kHz Oscillator Enable (write-protection bit)
1 = Enable 10 kHz Oscillation
0 = Disable 10 kHz Oscillation
Internal 22.1184 MHz Oscillator Enable (write-protection bit)
1 = Enable 22.1184 MHz Oscillation
0 = Disable 22.1184 MHz Oscillation
External 32.768 kHz Crystal Enable (write-protection bit)
1 = Enable external 32.768 kHz Crystal (Normal operation)
0 = Disable external 32.768 kHz Crystal
External 4~24 MHz Crystal Enable (write-protection bit)
The bit default value is set by flash controller user configuration register config0
[26:24]. When the default clock source is from external 4~24 MHz crystal, this bit is set
to 1 automatically
1 = Enable external 4~24 MHz crystal
0 = Disable external 4~24 MHz crystal
command
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Publication Release Date: Oct 22, 2010
Revision V1.06