NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 268

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.6
I
Register
I2CON
Bits
[31:8]
[7]
[6]
[5]
[4]
[3]
[2]
2
C Control Register (I2CON)
Register Description
31
23
15
EI
7
NuMicro™ NUC100 Series Technical Reference Manual
Offset
I2C_BA+0x00
Descriptions
Reserved
EI
ENSI
STA
STO
SI
AA
ENSI
30
22
14
6
R/W
R/W
Reserved
Enable Interrupt
1 = Enable I
0 = Disable I
I
1 = Enable
0 = Disable
Set to enable I
enables. The multi-function pin function of SDA and SCL must set to I
I
Setting STA to logic 1 to enter master mode, the I
repeat START condition to bus when the bus is free.
I
In master mode, setting STO to transmit a STOP condition to bus then I
will check the bus condition if a STOP condition is detected this bit will be cleared by
hardware automatically. In a slave mode, setting STO resets I
defined “not addressed” slave mode. This means it is NO LONGER in the slave
receiver mode to receive data from the master transmit device.
I
When a new I
hardware, and if bit EI (I2CON [7]) is set, the I
cleared by software. Clear SI is by writing 1 to this bit.
Assert Acknowledge Control Bit
When AA=1 prior to address or data received, an acknowledged (low level to SDA) will
STA
2
2
2
2
C Controller Enable Bit
C START Control Bit
C STOP Control Bit
C Interrupt Flag
29
21
13
5
Description
I
2
C Control Register
2
2
C interrupt
C interrupt
2
STO
C state is present in the I2CSTATUS register, the SI flag is set by
2
28
20
12
C serial function controller. When ENSI=1 the I
4
- 268 -
Reserved
Reserved
Reserved
27
19
11
SI
3
Publication Release Date: Dec. 22, 2010
AA
26
18
10
2
2
C interrupt is requested. SI must be
2
C hardware sends a START or
25
17
9
1
2
Reserved
C hardware to the
Revision V1.06
2
2
C serial function
C function first.
Reset Value
0x0000_0000
2
C hardware
24
16
8
0