NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 455

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.14.4 Functional Description
5.14.4.1 Communication
The PS/2 device implements a bidirectional synchronous serial protocol. The bus is "Idle" when
both lines are high (open-collector). This is the only state where the device is allowed start to
transmit DATA. The host has ultimate control over the bus and may inhibit communication at any
time by pulling the CLK line low.
The CLK signal is generated by PS2 device. If the host wants to send DATA, it must first inhibit
communication from the device by pulling CLK low. The host then pulls DATA low and releases
CLK. This is the "Request-to-Send" state and signals the device to start generating CLK pulses.
All data is transmitted one byte at a time and each byte is sent in a frame consisting of 11 or 12
bits. These bits are:
The parity bit is set if there is an even number of 1's in the data bits and cleared to 0 if there is an
odd number of 1's in the data bits. The number of 1's in the data bits plus the parity bit always add
up to an odd number set to 1. This is used for error detection. The device must check this bit and
if incorrect it should respond as if it had received an invalid command.
The host may inhibit communication at any time by pulling the CLK line low for at least 100
microseconds. If a transmission is inhibited before the 11th clock pulse, the device must abort the
current transmission and prepare to retransmit the current data when host releases Clock. In
order to reserve enough time for s/w to decode host command, the transmit logic is blocked by
RXINT bit, S/W must clear RXINT bit to start retransmit. S/W can write CLRFIFO to 1 to reset
FIFO pointer if need.
Device-to-Host
The device uses a serial protocol with 11-bit frames. These bits are:
The device writes a bit on the DATA line when CLK is high, and it is read by the host when CLK is
low. Figure 5-84 in the following illustrate this.
1 start bit. This is always 0
8 DATA bits, least significant bit first
1 parity bit (odd parity)
1 stop bit. This is always 1
1 acknowledge bit (host-to-device communication only)
1 start bit. This is always 0
8 DATA bits, least significant bit first
1 parity bit (odd parity)
1 stop bit. This is always 1
NuMicro™ NUC100 Series Technical Reference Manual
DATA
High
High
Low
CLK
High
Low
High
- 455 -
Bus State
Idle
Communication Inhibit
Host Request to Send
Publication Release Date: Oct 22, 2010
Revision V1.06