NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 562

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.8
6.8.1
The program memory and data flash supports both in hardware programming and in system
programming (ISP). Hardware programming mode uses gang-writers to reduce programming
costs and time to market while the products enter into the mass production state. However, if the
product is just under development or the end product needs firmware updating in the hand of an
end user, the hardware programming mode will make repeated programming difficult and
inconvenient. ISP method makes it easy and possible. NuMicro™ NUC100 Series supports ISP
mode allowing a device to be reprogrammed under software control. Furthermore, the capability
to update the application firmware makes wide range of applications possible.
ISP is performed without removing the microcontroller from the system. Various interfaces enable
LDROM firmware to get new program code easily. The most common method to perform ISP is
via UART along with the firmware in LDROM. General speaking, PC transfers the new APROM
code through serial port. Then LDROM firmware receives it and re-programs into APROM through
ISP commands. Nuvoton provides ISP firmware and PC application program for NuMicro™
NUC100 Series. It makes users quite easy perform ISP through Nuvoton ISP tool.
NuMicro™ NUC100 Series supports booting from APROM or LDROM initially defined by user
configuration bit (CBS). If user wants to update application program in APROM, he can write
BS=1 and starts software reset to make chip boot from LDROM. The first step to start ISP
function is write ISPEN bit to 1. S/W is required to write REGWRPROT register in Global Control
Register (GCR, 0x5000_0100) with 0x59, 0x16 and 0x88 before writing ISPCON register. This
procedure is used to protect flash memory from destroying owning to unintended write during
power on/off duration.
Several error conditions are checked after software writes ISPGO bit. If error condition occurs,
ISP operation is not been started and ISP fail flag will be set instead of. ISPFF flag is cleared by
s/w, it will not be over written in next ISP operation. The next ISP procedure can be started even
ISPFF bit keeps at 1. It is recommended that s/w to check ISPFF bit and clear it after each ISP
operation if it is set to 1.
When ISPGO bit is set, CPU will wait for ISP operation finish, during this period; peripheral still
keeps working as usual. If any interrupt request occur, CPU will not service it till ISP operation
finish. When ISP operation is finished, the ISPGO bit will be cleared by hardware automatically.
User can know if ISP operation is finished by checking this bit. User should add ISB instruction
next to the instruction which set 1 to ISPGO bit to ensure correct execution of the instructions
following ISP operation.
Note that NuMicro™ NUC100 Series allows user to update CONFIG value by ISP.
In System Program (ISP)
ISP Procedure
HREADY
HCLK
NuMicro™ NUC100 Series Technical Reference Manual
CPU writes ISPGO bit
CPU is halted but other peripherials keep working
- 562 -
ISP operation
Publication Release Date: Dec. 22, 2010
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Revision V1.06