NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 264

• Manufacturer Part Number: NUC100LC1BN
• Description: IC MCU 32BIT 32KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™r

Specifications of NUC100LC1BN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.6.4
5.6.4.1
5.6.4.2
The CPU interfaces to the I
(control register), I2CSTATUS (status register), I2CDAT (data register), I2CADDRn (address
registers, n=0~3), I2CADMn (address mask registers, n=0~3), I2CLK (clock rate register) and
I2CTOC (Time-out counter register). All bit 31~ bit 8 of these I
reserved. These bits do not have any functions and are all zero if read back.
When I
by I2CON and I
I2CSTATUS, the I
Interrupt bit EI (I2CON [7]) is set high at this time, the I
I2CSTATUS[7:3] stores the internal state code, the lowest 3 bits of I2CSTATUS are always zero
and the content keeps stable until SI is cleared by software. The base address is 4002_0000 and
4012_0000.
I
register are irrelevant when I
must be loaded with the chip’s own slave address. The I
I2CADDRn are matched with the received slave address.
The I
hardware will respond to General Call address (00H). Clear GC bit to disable general call
function.
When GC bit is set and the I
after Master send general call address to I
I
I2CADMn (n=0~3). When the bit in the address mask register is set to one, it means the received
corresponding address bit is don’t-care. If the bit is set to zero, that means the received
corresponding register bit should be exact the same as address register.
This register contains a byte of serial data to be transmitted or a byte which just has been
received. The CPU can read from or write to this 8-bit (I2CDAT [7:0]) directly while it is not in the
process of shifting a byte. when I
Data in I2CDAT [7:0] remains stable as long as SI bit is set. While data is being shifted out, data
on the bus is simultaneously being shifted in; I2CDAT [7:0] always contains the last data byte
present on the bus. Thus, in the event of arbitration lost, the transition from master transmitter to
slave receiver is made with the correct data in I2CDAT [7:0].
I2CDAT [7:0] and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled
by the I
acknowledge bit into I2CDAT [7:0] on the rising edges of serial clock pulses on the SCL line.
When a byte has been shifted into I2CDAT [7:0], the serial data is available in I2CDAT [7:0], and
the acknowledge bit (ACK or NACK) is returned by the control logic during the ninth clock pulse.
Serial data is shifted out from I2CDAT [7:0] on the falling edges of SCL clock pulses, and is
shifted into I2CDAT [7:0] on the rising edges of SCL clock pulses.
2
2
C port is equipped with four slave address registers I2CADDRn (n=0~3). The contents of the
C bus controllers support multiple address recognition with four address mask registers
Protocol Registers
Address Registers (I2CADDR)
2
Data Register (I2CDAT)
C ports support the “General Call” function. If the GC bit (I2CADDRn [0]) is set the I
2
C port is enabled by setting ENS1 (I2CON [6]) to high, the internal states will be controlled
2
C hardware and cannot be accessed by the CPU. Serial data is shifted through the
NuMicro™ NUC100 Series Technical Reference Manual
2
C logic hardware. Once a new status code is generated and stored in
2
C Interrupt Flag bit SI (I2CON [3]) will be set automatically. If the Enable
2
C port through the following thirteen special function registers: I2CON
2
2
C is in master mode. In the slave mode, the bit field I2CADDRn[7:1]
C is in Slave mode, it can receive the general call address by 00H
2
C is in a defined state and the serial interrupt flag (SI) is set.
2
C bus, then it will follow status of GC mode.
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2
C interrupt will be generated. The bit field
Publication Release Date: Dec. 22, 2010
2
C hardware will react if the contents of
2
C special function registers are
Revision V1.06
2
C port