NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 292

IC MCU 32BIT 32KB FLASH 48LQFP

NUC100LC1BN

Manufacturer Part Number
NUC100LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Datasheets

Specifications of NUC100LC1BN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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5.7.4.5
5.7.4.6
The Capture 0 and PWM 0 share one timer that included in PWM 0; and the Capture 1 and PWM
1 share another timer, and etc. The capture always latches PWM-counter to CRLRx when input
channel has a rising transition and latches PWM-counter to CFLRx when input channel has a
falling transition. Capture channel 0 interrupt is programmable by setting CCR0[1] (Rising latch
Interrupt enable) and CCR0[2] (Falling latch Interrupt enable) to decide the condition of interrupt
occur. Capture channel 1 has the same feature by setting CCR0[17] and CCR0[18], and etc.
Whenever the Capture controller issues a capture interrupt, the corresponding PWM counter will
be reloaded with CNRx at this moment. Note that the corresponding GPIO pins must be
configured as capture function (disable POE and enable CAPENR) for the corresponding capture
channel.
At this case, the CNR is 8:
There are eight PWM interrupts, PWM0_INT~PWM7_INT, which are divided into PWMA_INT and
1. The PWM counter will be reloaded with CNRx when a capture interrupt flag (CAPIFx) is
2. The channel low pulse width is (CNR + 1 - CRLR).
3. The channel high pulse width is (CNR + 1 - CFLR).
Capture Operation
PWM-Timer Interrupt Architecture
set.
NuMicro™ NUC100 Series Technical Reference Manual
Note: X=0~3
Capture Input x
PWM Counter
CAPCHxEN
CRL_IEx
CFL_IEx
CRLRIx
CAPIFx
CFLRIx
CRLRx
CFLRx
Figure 5-45 Capture Operation Timing
Set by H/W
Set by H/W
3
2
1
- 292 -
8
1
Reload
(If CNRx = 8)
Clear by S/W
Clear by S/W
7
Set by H/W
6
Publication Release Date: Dec. 22, 2010
5
8
Reload
5
Clear by S/W
7
No reload due to
no CAPIFx
6
7
5
Revision V1.06
4

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